What are the common methods for chip function testing? Recommended 6 simple and efficient methods

With the increasing demand for miniaturization of electronic devices, the functions of microcontrollers are also increasing. At present, in order to ensure the ...

Nov 07,2023 | Bonnie

With the increasing demand for miniaturization of electronic devices, the functions of microcontrollers are also increasing. At present, in order to ensure the quality of the chip, chip testing is usually carried out in the process from design to mass production. The traditional chip debugging technology is to add a set of function-oriented test program on the basis of the chip function, which can only detect the error or fault of the chip, and can not accurately locate the error on the chip terminal, and can only be judged according to the experience of the tester, which will lead to the slow and inefficient chip testing. Since each functional component has its own testing needs, design engineers must develop a test program in the early stages of design.

Chip Functional Test Methods

There are six commonly used methods for chip functional test: board-level test,wafer level testing wafer CP test, package product FT test, system-level SLT test and reliability test.

The first: board-level testing, the main technology applied to the social function of the test, the use of PCB board + chip to build their own a "simulation" of the chip design work and life environment, the chip's interfaces are cited to detect the function of the system chip, or in a variety of harsh environments to see the chip enterprise can be normal management work. The equipment to be applied is mainly analyzing instruments and meters, and what we need to make is mainly EVB evaluation boards.

Second, the system-level SLT test is commonly used in function, performance and reliability testing, often used as a complement to the completion of the FT test, as the name suggests, it is tested in the system environment, the chip into the normal operating environment to test its functionality, the disadvantage is that it can only cover part of the function, the coverage rate is low, so the FT is generally a complementary means.

Third: Reliability testing, mainly on the chip to impose a variety of harsh environments, such as ESD electrostatic, i.e., simulating the human body or industrial body on the chip to apply instantaneous large voltage.

Fourth: post-package FT test, usually used for functional testing, performance testing and reliability testing to check whether the chip functions properly and whether there are any defects in the packaging process, which also helps reliability testing to determine whether the chip is still working after the "firestorm".

The fifth type: wafer CP test, commonly used in functional testing and performance testing, wafer test to understand whether the chip function is normal, screening out the chip wafer fault chip.

Sixth: Multi-test.

Chip test equipment

The first: tester

The test machine is a specialized network device for detecting the main functions and performance of the system chip. When testing, the test machine to be tested chip to impose an input data signal, get to improve the output control signal and the expected value of the analysis and comparison, to determine the electrical performance of the Chinese chip and the effectiveness of the product service function. Within the CP and FT testing technology session, the test machine will transmit the results to the probe table and sorting machine respectively. When the probe table receives the information test research results, it will carry out the ink-jet operation to mark out the chips with defects on the wafer;failure analysis and when the sorter receives the results from the test machine, it will make reasonable rounding up and categorization of China's chips can be carried out.

Second: Probe machine

The probe table is used for CP testing after wafer processing and before packaging. It is responsible for the transportation and positioning of wafers so that the grains on the wafers are in contact with the probes and are tested one by one. The workflow of the Probe Station is: moving the wafer under the wafer camera by means of the slide table - obtaining an image of the wafer by means of the wafer camera to determine the position of the wafer - moving the probe camera under the probe card to position the probe --Move the wafer under the probe card --Finish by moving the slide table vertically.

Third: Sorting Machine

Sorting equipment is used for FT testing after chip packaging and is post-test equipment that provides chip screening and sorting functions. The sorter is responsible for delivering the incoming chips to the test module in accordance with the system's designed pick-and-place method to complete the circuit stress test. In this step, the sorter selects and classifies circuits according to the test results.

Chips, as the core components of electronic products, are becoming more and more delicate, and in order to ensure the quality of chips, effective testing techniques have been adopted to test the performance of chips. The wafer confirms that as the complexity of the design increases, the workload and operational difficulty increase by orders of magnitude. Through complex simulation of design engineering, verification personnel describe chip product specifications as various functions in the form of binary waveforms, process complex state spaces, and detect errors in them, which is the biggest challenge for verification engineers.

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